Energy Reduction in Application Specific Network-on-Chips Using Performance-Power Exchange

Networks-on-Chips (NoCs) are required not only to provide ultra-low latency, but also to consume as little energy as possible. Because higher energy consumption leads to decreased mission duration, increased heat dissipation and decreased reliability. This paper exploit the well-known Dynamic Voltage Scaling (DVS) technique to reduce consumed energy in an application specific NoC without any performance overhead. This method includes two steps. In the first step, extra virtual channels are exploited in the switching element of an NoC node to increase the performance of the network. In the second step, the performance gain achieved in the first step is used to exchange by lower energy consumption using the DVS technique. A flit level VHDL-based simulator and Synopsys Power Compiler tool have been used to extract experimental results. The simulation results show that the method can efficiently reduce the energy consumption of an NoC node at least 20%.